8

Architecture

The PFC and LLC external MOSFETs gates are managed by the “State Machine Event Driven” (SMEDs): 2 for

PFC (PFC SMEDs) and 2 for LLC (LLC SMEDs).

The SMEDs are programmable state machine driven by events:

•

External events

–

Analog comparators outputs

–

Power manager generated events (protections)

•

Internal events

–

Timer events

PFC SMEDs

•

Input events: PFC RECOT, PFC OC1, PFC ZCD

•

Outputs: PFC_GD

LLC SMEDs

•

Input events: LLC ZCD

•

Outputs: LVG, HVG

The µP subsystem dynamically manages the control loop.

•

Analog comparators thresholds setting

•

SMED configuration

•

SMED timers

•

ADC scheduler

•

Interrupt management

The multichannel ADC is controlled by a programmable event driven scheduler: sampling sequence can be

configured and every sample can be triggered by a specific SMED state occurrence and an internal timer value.

Different priorities can be programmed to allow fast sampling for real time control and slow sampling for state

control (i.e., temperature).

The scheduler can be programmed to generate interrupts after completion of selectable conversions.

A dedicated AC line monitor easily follows the AC line providing system triggers.

The µP reads data from the ADC and performs the loop calculation with the support of a dedicated 16-b x 16-b

multiplier and a 32-b accumulator unit.

A Power management and burst-mode machine manages the system power state in order to have very low

idle consumption and fast activity restart during the burst-mode operation.

Hard protections are managed with a very low propagation delay; the protection enable and the latched/not

latched response are programmable.

The power manager controls also the brown-in/out, VCC charge/discharge, AC monitor and X-cap discharge.

A Watchdog resets the system in case of missed µP signal for a long time.

A communication peripheral allows serial communication at startup and during the normal operation for:

•

External memory communication for

–

Black box external recording

–

Patch SW upload

•

Monitoring

•

Internal memory R/W and OTP management

•

Test mode

STNRG011

Architecture

DS12075 - Rev 4

page 13/31