| 전자부품 데이터시트 검색엔진 |
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ESD321DPYR 데이터시트(PDF) 5 Page - Texas Instruments |
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ESD321DPYR 데이터시트(HTML) 5 Page - Texas Instruments |
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5 / 25 page ![]() 6.6 Electrical Characteristics At TA = 25°C unless otherwise noted PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VRWM Reverse stand-off voltage IIO < 50 nA, across operating temperature range 3.6 V ILEAKAGE Leakage current at 3.6 V VIO = 3.6 V, I/O to GND 0.1 10 nA VBRF Breakdown voltage, I/O to GND (1) IIO = 1 mA 4.5 7.5 V VFWD Forward Voltage, GND to I/O (1) IIO = 1 mA 0.8 V VHOLD Holding voltage, I/O to GND (2) IIO = 1 mA 5.1 V VCLAMP Clamping voltage IPP = 6 A (8/20 µs Surge), I/O to GND 6.3 V IPP = 16 A (100 ns TLP), I/O to GND 6.8 V IPP = 16 A (100 ns TLP), GND to I/O 4.7 V RDYN Dynamic resistance I/O to GND, 100 ns TLP, between 10 to 20 A IPP 0.13 Ω GND to I/O , 100 ns TLP, between 10 to 20 A IPP 0.2 CLINE Line capacitance, IO to GND VIO = 0 V, Vp-p = 30 mV, f = 1 MHz 0.9 1.1 pF (1) VBRF and VBRR are defined as the voltage obtained at 1 mA when sweeping the voltage up, before the device latches into the snapback state (2) VHOLD is defined as the voltage when 1 mA is applied, after the device has successfully latched into the snapback state. www.ti.com ESD321 SLVSEN8A – JULY 2018 – REVISED DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: ESD321 |
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