t(B)

t(BR)

t(HW1)

t(HW0)

t(CYCH)

t(DW1)

t(DW0)

t(CYCD)

Break

7-bitaddress

8-bitdata

(a) BreakandBreakRecovery

(c) Host TransmittedBit

(d) Gauge TransmittedBit

(e) GaugetoHostResponse

1.2V

t(RISE)

(b) HDQlinerisetime

1-bit

R/W

t(RSPS)

Figure 6-1. Timing Diagrams

6.14 Timing Requirements: I2C-Compatible Interface

TA = –40°C to 85°C, 2.45 V < VREGIN = VBAT < 5.5 V; typical values at TA = 25°C and VREGIN = VBAT = 3.6 V (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

tr

SCL/SDA rise time

300

ns

tf

SCL/SDA fall time

300

ns

tw(H)

SCL pulse width (high)

600

ns

tw(L)

SCL pulse width (low)

1.3

μs

tsu(STA)

Setup for repeated start

600

ns

td(STA)

Start to first falling edge of SCL

600

ns

tsu(DAT)

Data setup time

100

ns

th(DAT)

Data hold time

0

ns

tsu(STOP)

Setup time for stop

600

ns

tBUF

Bus free time between stop and start

66

μs

fSCL

Clock frequency

400

kHz

tSU(STA)

SCL

SDA

tw(H)

tw(L)

tf

tr

t(BUF)

tr

td(STA)

REPEATED

START

th(DAT)

tsu(DAT)

tf

tsu(STOP)

STOP

START

Figure 6-2. I2C-Compatible Interface Timing Diagrams

BQ34Z100-R2

SLUSF37 – DECEMBER 2022

www.ti.com

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