ST7LNB0 datasheet(16/22 Pages) STMICROELECTRONICS

16 / 22 page

ST7LNB0

16/22

6.7 CONTROL PIN CHARACTERISTICS

6.7.1 Asynchronous RESET Pin

Notes:

1. Data based on characterization results, not tested in production.

2. The IIO current sunk must always respect the absolute maximum rating specified in Section 6.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS.

3. The RON pull-up equivalent resistor is based on a resistive transistor. Specified for voltage on RESET pin between

VILmax and VDD

4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

5. The reset network protects the device against parasitic resets.

6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below

the VIL max. level specified in section 6.7.1 on page 16. Otherwise the reset will not be taken into account internally.

8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure

that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value

specified for IINJ(RESET) in section 6.2.2 on page 9.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage

0.3xVDD

VIH

Input high level voltage

0.7xVDD

Vhys

Schmitt trigger voltage hysteresis 1)

VOL

Output low level voltage 2)

VDD=5V

IIO=+5mA

0.5

1.0

IIO=+2mA

0.2

0.4

RON

Pull-up equivalent resistor 3) 1)

VDD=5V

Ω

tw(RSTL)out Generated reset pulse duration

Internal reset sources

µs

th(RSTL)in External reset pulse hold time

µs

tg(RSTL)in Filtered glitch duration

200

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