Data Sheet AS1100

Revision 1.32, Oct. 2004

Page 3 of 12

Parameter

Symbol Conditions

Min

Typ

Max

Units

Input Current DIN, CLK, LOAD

-1

1

µA

Logic High Input Voltage

3.5

V

Logic Low Input Voltage

0.8

V

Output High Voltage

VDD - 1

V

Output Low Voltage

0.4

V

Hysteresis Voltage

DIN, CLK, LOAD

1

V

Timing Characteristics

CLK Clock Period

100

ns

CLK Pulse Width High

50

ns

CLK Pulse Width Low

50

ns

CLK Rise to LOAD Rise Hold

Time

0ns

DIN Setup Time

25

ns

DIN Hold Time

0ns

Output Data Propagation Delay

25

ns

LOAD Rising Edge to Next

Clock Rising Edge

50

ns

Minimum LOAD Pulse High

50

ns

Data-to-Segment Delay

2.25

ms

Pin Description

Pin

Name

Function

1

DIN

Data input. Data is programmed into the 16Bit shift register on the rising CLK edge

2, 3, 5–8, 10,

11

DIG 0–DIG 7

8 digit driver lines that sink the current from the common cathode of the display.

In shutdown mode the AS1100 switches the outputs to VDD

4, 9

GND

both GND pins must be connected

12

LOAD

Strobe input. With the rising edge of the LOAD signal the 16 bit of serial data is latched into

the register.

13

CLK

Clock input. The interface is capable to support clock frequencies up to 10MHz. The serial

data is clocked into the internal shift register with the rising edge of the CLK signal. On the

DOUT pin the data is applied with the falling edge of CLK.

14–17, 20–23

SEG A–G,

DP

Seven segment driver lines including the decimal point. When a segment is turned off the

output is connected to GND.

18

ISET

brightness.

19

VDD

Positive Supply Voltage (+5V)

24

DOUT

Serial data output for cascading drivers. The output is valid after 16.5 clock cycles. The

output is never set to high impedance.