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BT817/8 Advanced Embedded Video Engine Datasheet

Version 1.1

Document No.: BRT_000302 Clearance No.: BRT#154

VCCIO3

1.8V, or 2.5V, or

3.3V

Supply for NOR Flash interface I/O pins

VCCA

3.3V

Supply for AUDIO_L pin and ADC circuit

VCC

3.3V

Supply for 3.3V circuits and internal 1.2V regulator

VOUT1V2,

VCC1V2

1.2V

Supply for digital core. Generated by internal regulator

Table 4-22 Power Supply

4.9.2

Internal Regulator and POR

The internal regulator outputs 1.2V to supply power to the core circuit.

The internal regulator requires a compensation capacitor (minimum 3.3uF) to be stable. A typical

design uses a 4.7uF or 10uF capacitor between the VOUT1V2 and GND pins. Do not connect any

other load to the VOUT1V2 pin.

The internal regulator will generate a Power-On-Reset (POR) pulse when the output voltage rises

above the POR threshold. The POR will reset all the core digital circuits.

4.9.3

Power Modes

When the supply to VCCIO and VCC is applied, the internal regulator is powered by VCC. An internal

POR pulse will be generated during the regulator power up until it is stable. After the initial power

up, the BT817/8 will stay in the SLEEP state. When needed, the host can set the BT817/8 to the

ACTIVE state by performing a SPI ACTIVE command. The graphics engine, the audio engine and the

touch engine are only functional in the ACTIVE state. To save power the host can send a command

to put the BT817/8 into any of the low power modes: STANDBY, SLEEP and POWERDOWN. In

addition, the host is allowed to put the BT817/8 in POWERDOWN mode from ACTIVE mode by

driving the PD_N pin to low. Refer to Figure 4-10 for the power state transitions.

Figure 4-10 Power State Transition

POWERDOWN

SLEEP

STANDBY

VCC/VCCIO

Power ON

Command

“PWRDOWN”

ACTIVE

Command

“PWRDOWN”

Command “STANDBY”

Command

“SLEEP”

Command

“ACTIVE”

Command

“ACTIVE”

Command

“PWRDOWN”

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