AP64352

Document number: DS41978 Rev. 5 - 2

15 of 21

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August 2019

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AP64352

Application Information (cont.)

12

Programming Switching Frequency

The switching frequency of the AP64352 can be programmed through either of two modes, Resistor Timing or External Clock Synchronization.

In Resistor Timing mode, a resistor is placed between the RT/CLK pin to ground and sets the switching frequency over a wide range from 100kHz

to 2.2MHz. The RT/CLK pin voltage is typically 0.5V. The RT/CLK pin cannot be left floating. The RT resistance required for a given switching

frequency is calculated by:

Eq. 8

Where:



RT is the resistance in kΩ



fsw is the switching frequency in kHz between 100kHz to 2.2MHz

FSS is enabled when programming the switching frequency through Resistor Timing mode.

In External Clock Synchronization mode, the switching frequency synchronizes to an external clock applied to the RT/CLK pin. The

synchronization frequency range is also 100kHz to 2.2MHz, and the rising edge of SW synchronizes to the falling edge of the external clock at the

RT/CLK pin with a typical 66ns delay. An internal PLL locks the internal switching frequency to that of the external clock signal. An external square

wave clock signal supplied at the RT/CLK pin must have a logic high level greater than 3.5V, a logic low level less than 0.4V, and a pulse width of

at least 80ns.

FSS is disabled when programming the switching frequency through External Clock Synchronization mode.

RT

RT/CLK

External

Clock

Oscillator

with PLL

CLK

Figure 25. Switching Between Resistor Timing and External Clock Synchronization Modes

In applications where both Resistor Timing and External Clock Synchronization modes are required, the device can be configured as shown in

Figure 25. Before an external clock signal is available at the RT/CLK pin, the device operates in Resistor Timing mode. When an external clock is

supplied to the RT/CLK pin, the device automatically transitions from Resistor Timing mode to External Clock Synchronization mode typically

within 85

μs. When the external clock signal is disconnected from the RT/CLK pin, the device’s switching frequency returns to being programmed

in Resistor Timing mode. When switching between Resistor Timing and External Clock Synchronization modes, it is recommended that the

external clock signal is within ±25% of the frequency controlling the device in Resistor Timing mode to prevent large changes in switching

frequency within the device.