Logic Cell Options

The ATV5000 logic cells contain most of the chip’s logic op-

tions. The standard logic cell contains two flip-flops, three sum

terms and three array inputs. The three sum terms can be com-

bined to provide sum term options of four, five, nine, or 13 prod-

uct terms. A combinatorial signal or the output of Q1 can be sent

to the I/O cell.

The ATV5000 retains the ATV2500’s ability to bury both reg-

isters in the I/O cell and still output a combinatorial signal (see

Figure 8). A new feature, unique to the ATV5000, is the ability

to output Q1 and feedback the combinatorial term directly (see

Figure 7). This high speed logic expansion term increases the

devices flexibility and gate utilization.

Buried Logic Cells

Each quadrant has six buried logic cells (see Figure 4). Each cell

contains one sum term with five product terms, a flip-flop, and

individual preset, clear, and clock terms. A configuration bit se-

lects either the Q output or the D input for feedback into the

regional bus.

CK1

AP1

AR2

CK2

Q1

AP2

AR1

R

R

R

U

U

U

U

R

R

R

U

R

R

R

U

U

U

U

R

Q2

CLOCK

OPTION

D2/T2

TO

I/O

CELL

D1/T1

R

R

R

R

U

U

Q2

Q1

OPTION

CLOCK

B

A

C

Logic Cell with Buried Sum Term and

Register to I/O Cell

Figure 7

0/1

LCKn

SELECT

LOGIC

TO

CELL

FROM

LOGIC

CELL

D

Q

I/O

U

OE

C

I/O Pin Logic

Figure 6

CK1

AR1

AP1

U

R

U

U

R

R

U

R

Q1

D1/T1

OPTION

CLOCK

R

R

SELECT

Buried Logic Cells

Figure 4

SELECT

LOGIC

TO

CELL

CLOCK

PRODUCT

TERM

RCKn

Clock Option

Figure 5

Flip-Flop Clock Options

Each register may be connected to its regional clock to provide

fast clock-to-output timing (see Figure 5). In this "synchronous"

mode, the clock is one of four input pins, a unique clock pin for

each chip quadrant. One product term defines each flip-flop’s

clock in the "asynchronous" mode.

In the "synchronous" mode, the regional clock is ANDed with

the product term. This provides the fast timing of a synchronous

clock with the local control of the product term.

I/O Pin Latches

Each I/O pin of the ATV5000 has an input latch which can be

individually enabled or disabled (see Figure 6). Each chip quad-

rant has a unique latch clock. When the latch is inactive, pin

input flows directly into the array. When activated, the latch is

flow-through when the clock signal is low, and data is captured

on the clock’s rising edge.

Flip-Flop Types

Each flip-flop in the ATV5000 may be configured as either a T-

or D-type flip-flop. A T-type flip-flop can also easily be config-

ured into a JK or SR flip-flop.

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ATV5000/L