SST26WF040B datasheet(31/96 Pages) MICROCHIP

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 2014-2017 Microchip Technology Inc.

DS20005283C-page 31

SST26WF040B/040BA SST26WF080B/080BA

5.29

Read-Status Register (RDSR) and

Read-Configuration Register

(RDCR)

The Read-Status Register (RDSR) and Read Configu-

ration Register (RDCR) commands output the contents

of the Status and Configuration registers. These com-

mands function in both SPI and SQI modes. The Status

operation. When a Write is in progress, poll the BUSY

bit before sending any new commands to assure that

the new commands are properly received by the

device.

To Read the Status or Configuration registers, the host

drives CE# low, then sends the Read-Status-Register

command cycle (05H) or the Read Configuration Reg-

ister command (35H). A dummy cycle is required in

SQI mode. Immediately after the command cycle, the

device outputs data on the falling edge of the SCK sig-

nal. The data output stream continues until terminated

by a low-to-high transition on CE#. See Figures 5-28

and 5-29 for the RDSR instruction sequence.

FIGURE 5-28:

READ-STATUS-REGISTER AND READ CONFIGURATION REGISTER

SEQUENCE (SQI)

FIGURE 5-29:

READ-STATUS-REGISTER AND READ CONFIGURATION REGISTER

SEQUENCE (SPI)

20005283 F11.0

MODE 3

SCK

SIO(3:0)

CE#

C1 C0

MODE 0

MSN LSN

H0 L0

Dummy

Status Byte Status Byte

Status Byte

Note: MSN = Most Signifi-

cant Nibble; LSN = Least Significant Nibble, C[1:0]=05H or 35H

20005283 F62.1

MODE 3

SCK

CE#

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

05 or 35H

MODE 0

HIGH IMPEDANCE

Status or Configuration

MSB

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