XRT83SL28IV datasheet(37/47 Pages) EXAR

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XRT83SL28

REV. 1.0.0

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

TABLE 7: MICROPROCESSOR REGISTER 0X00H BIT DESCRIPTION

GLOBAL CONTROL REGISTER FOR ALL 8 CHANNELS (0X00H)

BIT

NAME

FUNCTION

Type

Default

Value

(HW reset)

GIE

Global Interrupt Enable

The global interrupt enable is used to enable/disable all interrupt

activity for all 8 channels. This bit must be set "High" for the inter-

rupt pin to operate.

"0" = Disable all interrupt generation

"1" = Enable interrupt generation to the individual channel registers

R/W

SR/DR

Single Rail / Dual Rail Select

This bit is used to configure the receive outputs and transmit inputs

to single rail or dual rail data formats.

"0" = Dual Rail

"1" = Single Rail

R/W

CODE

Encoding / Decoding Select (Single Rail Mode Only)

This bit is used to select between AMI or HDB3.

"0" = HDB3

"1" = AMI

R/W

RCLKinv

Receiver Clock Data

"0" = RPOS/RNEG data is updated on the rising edge of RCLK

"1" = RPOS/RNEG data is updated on the falling edge of RCLK

R/W

TCLKinv

Transmitter Clock Data

"0" = TPOS/TNEG data is sampled on the falling edge of TCLK

"1" = TPOS/TNEG data is sampled on the rising edge of TCLK

R/W

FIFOS

FIFO Depth Select

The FIFO depth select is used to configure the part for a 32-bit or

64-bit FIFO (Within the Jitter Attenuator Block). The delay of the

FIFO is typically equal to ½ the FIFO depth.

"0" = 32-bit FIFO

"1" = 64-bit FIFO

R/W

JASEL1

JASEL0

Jitter Attenuator Select

These bits are used to configure the Jitter Attenuator into the

Receive or Transmit path.

"00" = Disabled

"01" = Transmit Path

"10" = Receive Path

"11" = Disabled

R/W

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