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ADC12DL080 데이터시트(PDF) 8 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
부품명 ADC12DL080
상세설명  Dual 12-Bit, 80 MSPS, A/D Converter for IF Sampling
PDF  24 Pages
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제조업체  NSC [National Semiconductor (TI)]
홈페이지  http://www.national.com
Logo NSC - National Semiconductor (TI)

ADC12DL080 데이터시트(HTML) 8 Page - National Semiconductor (TI)

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DC and Logic Electrical Characteristics (Continued)
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V
A =VD = +3.3V, VDR =
+2.5V, PD = 0V, External V
REF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface
limits apply for T
J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
POWER SUPPLY CHARACTERISTICS
I
A
Analog Supply Current
PD Pin = DGND, V
REF =VA
PD Pin = V
D
112.5
15
136
mA (max)
mA
I
D
Digital Supply Current
PD Pin = DGND
PD Pin = V
D ,fCLK =0
23
0
26
mA (max)
mA
I
DR
Digital Output Supply Current
PD Pin = DGND, C
L = 10 pF (Note 14)
PD Pin = V
D,fCLK =0
15
0
mA
mA
Total Power Consumption
PD Pin = DGND, C
L = 10 pF (Note 15)
PD Pin = V
D
447
50
535
mW (max)
mW
PSRR
Power Supply Rejection Ratio
Rejection of Full-Scale Error with
V
A = 3.0V vs. 3.6V
80
dB
AC Electrical Characteristics
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, V
A =VD = +3.3V, VDR =
+2.5V, PD = 0V, External V
REF = +1.0V, fCLK = 80 MHz, fIN = 40 MHz, CL = 10 pF/pin, Duty Cycle Stabilizer On. Boldface
limits apply for T
J =TMIN to TMAX: all other limits TJ = 25˚C (Notes 7, 8, 9, 12)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 10)
Units
(Limits)
f
CLK1
Maximum Clock Frequency
80
MHz (min)
f
CLK2
Minimum Clock Frequency
10
MHz
t
CH
Clock High Time
Duty Cycle Stabilizer On
6.25
3.75
ns (min)
t
CL
Clock Low Time
Duty Cycle Stabilizer On
6.25
3.75
ns (min)
t
CH
Clock High Time
Duty Cycle Stabilizer Off
6.25
5
ns (min)
t
CL
Clock Low Time
Duty Cycle Stabilizer Off
6.25
5
ns (min)
t
r,tf
Clock Rise and Fall Times
2
ns (max)
t
CONV
Conversion Latency
7
Clock
Cycles
t
OD
Data Output Delay after Rising
Clock Edge
7.5
3.5
ns (min)
11
ns (max)
t
OSU
Output Set up time from data
output transition to rising edge of
DRDY
(Note 17)
7.2
4
ns (min)
t
OH
Output Hold time from rising edge
of DRDY to next data output
transition
(Note 17)
5.3
4
ns (min)
t
AD
Aperture Delay
2
ns
t
AJ
Aperture Jitter
0.3
ps rms
t
DIS
Data outputs into Hi-Z Mode
10
ns
t
EN
Data Outputs Active after Hi-Z
Mode
10
ns
t
PD
Power Down Mode Exit Cycle
0.1 µF on pins 4,5,6,12,13,14; 10 µF
between pins 5, 6 and between pins
12, 13
100
µs
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
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