DS1963L

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ADDRESS REGISTERS Figure 6

T7

T6

T5

T4

T3

T2

T1

T0

T15

T14

T13

T12

T11

T10

T9

T8

AA

1)

PF

E4

E3

E2

E1

E0

1)

THIS BIT WILL ALWAYS BE 0.

Read Memory + Counter [A5H]

The Read Memory + Counter command is used to read memory data together with the write cycle counter

associated with the addressed page of data memory. The additional information is transmitted by the

DS1963L as the end of a memory page is encountered. Following the current value of the page write

cycle counter the DS1963L transmits 32 tamper-detect bits and a 16-bit CRC generated by the DS1963L.

The tamper-detect bits are factory-preset to 55555555H and locked. Tampering with the device will

change this data pattern.

After having sent the command code of the Read Memory + Counter command, the bus master sends a 2-

byte address (TA1=(T7:T0), TA2=(T15:T8)) that indicates a starting byte location within the data field.

With the subsequent read data time slots the master receives data from the DS1963L starting at the initial

address and continuing until the end of a 32-byte page is reached. At that point the bus master will send

80 additional read data time slots and receive the contents of the 32-bit write cycle counter associated

with the addressed page, the status of the 32 tamper-detect bits and a 16-bit CRC. With subsequent read

data time slots the master will receive data starting at the beginning of the next page followed again by

the contents of the page write cycle counter, tamper-detect bits and CRC for that page. This sequence will

continue until the final page and its accompanying data are read by the bus master. When applying the

Read Memory + Counter command to a page that does not have a page write cycle counter associated, the

master will read FFFFFFFFH instead of a valid cycle count.

With the initial pass through the Read Memory + Counter flow chart the 16-bit CRC value is the result of

shifting the command byte into the cleared CRC generator, followed by the 2 address bytes, the contents

of the data memory, the write page cycle counter and the tamper-detect bits. Subsequent passes through

the Read Memory + Counter flow chart will generate a 16-bit CRC that is the result of clearing the CRC

generator and then shifting in the contents of the data memory page, its associated page write cycle

counter and tamper-detect bits. After the 16-bit CRC of the last page is read, the bus master will receive

logical 1’s from the DS1963L until a Reset Pulse is issued. The Read Memory + Counter command

sequence can be ended at any point by issuing a Reset Pulse.

TARGET ADDRESS (TA1)

TARGET ADDRESS (TA2)

ENDING ADDRESS WITH

DATA STATUS (E/S)

(READ ONLY)