NXP Semiconductors

FS8600_SDS

Fail-safe system basis chip with multiple SMPSs and LDOs

• Logical and analog built-in self-test (LBIST, ABIST)

• Safety outputs with latent fault detection mechanism (PGOOD, RSTB, FS0B)

Configuration and Enablement

• QFN 48 pins with exposed pad for optimized thermal management

• OTP programming for device customization

3 Applications

• Domain controller (ADAS, electrification, infotainment, etc.)

• Radar (radar, imaging radar)

• Vision (mono camera, stereo camera, night vision, etc.)

• 24 V battery network (60 V maximum): Truck, bus, transportation

• 12 V battery network (36 V maximum): Automotive

4 Simplified Application Diagram

aaa-047804

MCU

VPRE

WAKE

Fail-safe

state machine

BOOST

To CAN Phy

ERRMON from PF50 PGOOD

VMON0_I2C from BUCK

VMON1_DAC from VCORE

VMON2-3_DAC from ext. REG

VMON4_RINT from LDO2

VMON5_RES from LDO1

VMON6_RES from VPRE

VMON7_RES from BOOST

VMON8-9_RES from ext. REG

WAKE2

WAKE1

PGOOD to ERRMON

To VMON1_DAC

VCORE

XFAILB

VPRE

To system load

FIN

INTB

PGOOD, RSTB

FCCU2 from MCU

FCCU1 from MCU

FS0B

System safe state

I2C

4x BUCKs in

multiphase

FS86

PF50

LDO2

VBAT

LDO1

BUCK

AMUX

Clock management

I2C

I2C for

watchdog monitoring

Figure 1. Simplified application diagram

FS8600_SDS

All information provided in this document is subject to legal disclaimers.

© 2022 NXP B.V. All rights reserved.

Product short data sheet

Rev. 2.0 — 7 December 2022

3 / 16