전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

74ALVT16841 데이터시트(PDF) 2 Page - NXP Semiconductors

부품명 74ALVT16841
상세설명  2.5V/3.3V ALVT 20-bit bus interface latch 3-State
PDF  14 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  PHILIPS [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74ALVT16841 데이터시트(HTML) 2 Page - NXP Semiconductors

  74ALVT16841 Datasheet HTML 1Page - NXP Semiconductors 74ALVT16841 Datasheet HTML 2Page - NXP Semiconductors 74ALVT16841 Datasheet HTML 3Page - NXP Semiconductors 74ALVT16841 Datasheet HTML 4Page - NXP Semiconductors 74ALVT16841 Datasheet HTML 5Page - NXP Semiconductors 74ALVT16841 Datasheet HTML 6Page - NXP Semiconductors 74ALVT16841 Datasheet HTML 7Page - NXP Semiconductors 74ALVT16841 Datasheet HTML 8Page - NXP Semiconductors 74ALVT16841 Datasheet HTML 9Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 2 / 14 page
background image
Philips Semiconductors
Product specification
74ALVT16841
2.5V/3.3V 20-bit bus interface latch (3-State)
2
1998 Feb 13
853-1868 18961
FEATURES
• High speed parallel latches
• 5V I/O Compatible
• Live insertion/extraction permitted
• Extra data width for wide address/data paths or buses carrying
parity
• Power-up 3-State
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are
required with MOS microprocessors
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
• Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
• ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ALVT16841 Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity. It is
designed for VCC operation at 2.5V or 3.3V with I/O compatibility to
5V.
The 74ALVT16841 consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is High. This allows asynchronous operation, as
the output transition follows the data in transition. On the nLE
High-to-Low transition, the data that meets the setup and hold time
is latched.
Data appears on the bus when the Output Enable (nOE) is Low.
When nOE is High the output is in the High-impedance state.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
SYMBOL
PARAMETER
Tamb = 25°C
2.5V
3.3V
UNIT
tPLH
tPHL
Propagation delay
nDx to nQx
CL = 50pF
1.8
2.1
1.5
1.7
ns
CIN
Input capacitance DIR, OE
VI = 0V or VCC
3
3
pF
COut
Output pin capacitance
VI/O = 0V or VCC
9
9
pF
ICCZ
Total supply current
Outputs disabled
40
70
µA
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
DWG NUMBER
56-Pin Plastic SSOP Type III
–40
°C to +85°C
74ALVT16841 DL
AV16841 DL
SOT371-1
56-Pin Plastic TSSOP Type II
–40
°C to +85°C
74ALVT16841 DGG
AV16841 DGG
SOT364-1



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com