Philips Semiconductors

Product specification

74F174

Hex D flip-flop

2

October 7, 1988

853–0060 94766

FEATURES

DESCRIPTION

The 74F174 has six edge-triggered D-type flip-flops with individual D

inputs and Q outputs. The common buffered Clock (CP) and Master

Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered. The state of each D input, one

setup time before the Low-to-High clock transition is transferred to

the corresponding flip-flop’s Q output.

All Q outputs will be forced Low independent of Clock or Data inputs

by a Low voltage level on the MR input. The device is useful for

applications where true outputs only are required, and the Clock and

Master Reset are common to all storage elements.

TYPE

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F174

100MHz

35mA

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

Q2

Q4

D3

Q3

D4

Q5

D5

MR

Q0

D2

D0

D1

Q1

9

8

GND

CP

SF00188

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

16-pin plastic DIP

N74F174N

SOT38-4

16-pin plastic SO

N74F174D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

D0–D5

Data inputs

1.0/1.0

20

µA/0.6mA

CP

Clock Pulse input (active rising edge)

1.0/1.0

20

µA/0.6mA

MR

Master Reset input (active-Low)

1.0/1.0

20

µA/0.6mA

Q0–Q5

Outputs

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

Q2

Q3

Q4

Q5

710

12

15

34

6

GND = Pin 8

SF00189

Q1

5

Q0

2

9

1

CP

MR

D0

D1

D2

D3

D4

D5

11

13

14

IEC/IEEE SYMBOL

SF00190

3

1D

9

C1

1

R

4

6

11

13

14

2

5

7

10

12

15