KSZ9567RTXI datasheet(65/232 Pages) MICROCHIP

65 / 232 page

 2017-2019 Microchip Technology Inc.

DS00002329D-page 65

KSZ9567R

4.13.3

REDUCED GIGABIT MEDIA INDEPENDENT INTERFACE (RGMII)

RGMII provides a common interface between RGMII PHYs and MACs, and has the following key characteristics:

• Pin count is reduced from 24 pins for GMII to 12 pins for RGMII.

• All speeds (10Mbps, 100Mbps and 1000Mbps) are supported at both half- and full-duplex.

• Data transmission and reception are independent and belong to separate signal groups.

• Transmit data and receive data are each four bits wide - a nibble.

In RGMII operation, the RGMII pins function as follows:

• The MAC sources the transmit reference clock, TX_CLKx, at 125MHz for 1000Mbps, 25MHz for 100Mbps, and

2.5MHz for 10Mbps.

• The PHY recovers and sources the receive reference clock, RX_CLKx, at 125MHz for 1000Mbps, 25MHz for

100Mbps, and 2.5MHz for 10Mbps.

• For 1000BASE-T, the transmit data, TXDx_[3:0], is presented on both edges of TX_CLKx, and the received data,

RXDx_[3:0], is clocked out on both edges of the recovered 125MHz clock, RX_CLKx.

• For 10BASE-T/100BASE-TX, the MAC holds TX_CTLx low until both the PHY and MAC operate at the same

speed. During the speed transition, the receive clock is stretched on either a positive of neagative pulse to ensure

that no clock glitch is presented to the MAC.

• TX_ERx and RX_ERx are combined with TX_ENx and RX_DVx, respectively, to form TX_CTLx and RX_CTLx.

These two RGMII control signals are valid at the falling clock edge.

After power-up or reset, the device is configured to RGMII mode if the appropriate configuration strap pins are set to

one of the RGMII mode capability options. Refer to Section 3.2.1, "Configuration Straps," on page 16 for available

options. Note that there is no mechanism for the RGMII interface to adapt its speed automatically to the speed of the

connected RGMII device. A configuration strap option sets the speed of each RGMII interface at power-up to either

1000Mbps or 100Mbps. For each port, a control register can override the configuration strap option and set the RGMII

speed to either 1000, 100 or 10Mbps. If a PHY is connected to an RGMII port, it should be ensured that the PHY link

speed is fixed in order to avoid a mismatch to the RGMII speed.

The device provides the option to add a minimum of 1.5ns internal delay to either TX_CLKx or RX_CLKx, via the RGMII

Internal Delay control bits in the XMII Port Control 1 Register. This can reduce or eliminate the need to add trace delay

to the clock signals on the printed circuit board. RGMII_ID_ig enables delay on TX_CLKx, and the default is off.

RGMII_ID_eg enables delay on RX_CLKx, and the default is on. Users should also be aware of any internal clock delay

that may be added by the connected RGMII device.

TABLE 4-32:

RMII CONNECTION TO EXTERNAL PHY

RMII Interface Signals Description

KSZ9567R Signals

External PHY Device Signals

Transmit Enable

RX_DVx (output)

TX_EN (input)

Transmit Data Bits [1:0]

RXDx_[1:0] (output)

TXD[1:0] (input)

Reference Clock

REFCLKIx (input)

or REFCLKOx (output)

REF_CLK

(input or output)

Carrier Sense Data Valid

TX_ENx (input)

CRS_DV (output)

Receive Error

No connection

RX_ER (output)

Receive Data Bits [1:0]

TXDx_[1:0] (input)

RXD[1:0] (output)

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