Philips Semiconductors

Product specification

74F283

4-bit binary full adder with fast carry

1989 Mar 03

4

Figure A shows how to make a 3-bit adder. Tying the operand inputs

of the fourth adder (A3, B3) Low makes

Σ3 dependent only on, and

equal to, the carry from the third adder. Using somewhat the same

principle, Figure B shows a way of dividing the 74F283 into a 2-bit

and a 1-bit adder. The third stage adder (A2, B2,

Σ2) is used as

means of getting a carry (C10) signal into the fourth stage adder (via

A2 and B2) and bringing out the carry from the second stage on

Σ2.

Note that as long as A2 and B2 are the same, whether High or Low,

they do not influence

Σ2. Similarly, when A2 and B2 are the same,

the carry into the third stage does not influence the carry out of the

third stage. Figure C shows a method of implementing a 5-input

encoder where the inputs are equally weighted. The outputs

Σ0, Σ1

and

Σ2 present a binary number of inputs I0–I4 that are true.

Figure D shows one method of implementing a 5-input majority gate.

When three or more of the inputs I0–I4 are true, the output M4 is

true.

APPLICATIONS

Σ1

Σ0

A0 B0 A1 B1 A2 B2 A3 B3

SF00856

Σ3

Σ2

L

C3

A.

3-bit Adder

Σ1

Σ0

A0 B0 A1 B1 A2 B2 A3 B3

Σ3

Σ2

B.

2-bit and 1-bit Adder

A0 B0 A1 B1

C10

A10 B10

Σ1

Σ0

Σ10

C2

Σ1

Σ0

A0 B0 A1 B1 A2 B2 A3 B3

Σ3

Σ2

C.

5-input Encoder

Σ1

Σ0

A0 B0 A1 B1 A2 B2 A3 B3

Σ3

Σ2

D.

5-input Majority Gate

I0

I1

I2

I3

I4

I0

I1

I2

I3

I4

L

M4