Philips Semiconductors

Product specification

74F382

Arithmetic logic unit

2

1990 Jul 12

853–0419 99966

FEATURES

DESCRIPTION

The 74F382 performs three arithmetic and three logic operations on

two 4-bit words, A and B. Two additional Select (S0–S2) input codes

force the Function outputs Low or High. An overflow output is

provided for convenience in Two’s Complement arithmetic.

A carry output is provided for ripple expansion. For high-speed

expansion using a carry look-ahead generator, refer to the 74F381

data sheet.

Signals applied to the Select inputs, S0–S2, determine the mode of

operation, as indicated in the Function Select Table. An extensive

listing of input and output levels is shown in the Function Table. The

circuit performs the arithmetic functions for either active-HIgh or

active-Low operands, with output levels in the same convention. In

the subtract operating modes, it is necessary to force a carry (High

for active-HIgh operands, Low for active-Low operands) into the Cn

input of the least significant package. Ripple expansion is illustrated

in Figure 1. The overflow output OVR is the Exclusive-OR of Cn+3

and Cn+4; a High signal on OVR indicates overflow in Two’s

complement operation (See Table 2 for Two’s complement

arithmetic). Typical delays for Figure 1 are given in Table 1. When

the 74F382 is cascaded to handle word lengths longer than 4 bits,

only the most significant overflow (OVR) output is used.

PIN CONFIGURATION

20

19

18

17

16

15

14

7

6

5

4

3

2

1

13

8

VCC

A1

B1

A0

B0

S0

S1

S2

F0

F1

GND

A2

B2

A3

B3

Cn

Cn+4

OVR

F3

F2

SF00935

12

9

11

10

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL SUPPLY

CURRENT (TOTAL)

74F382

7.0ns

54mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

20-pin plastic DIP

N74F382N

SOT146-1

20-pin plastic SO

N74F382D

SOT163-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

A0 – A3

A operand inputs

1.0/4.0

20

µA/2.4mA

B0 – B3

B operand inputs

1.0/4.0

20

µA/2.4mA

S0 – S2

Function select inputs

1.0/1.0

20

µA/0.6mA

Cn

Carry input

1.0/5.0

20

µA/3.0mA

Cn+4

Carry output

50/33

1.0mA/20mA

OVR

Overflow output

50/33

1.0mA/20mA

F0–F3

Outputs

50/33

1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as 20

µA in the High state and 0.6mA in the Low state.