Philips Semiconductors

Product specification

74F597

8-bit shift register with input storage registers

2

1991 Sep 13

853–1556 03964

FEATURES

(20

µA in High and Low states)

when SHCP is High

DESCRIPTION

The 74F597 consists of an 8-bit storage register feeding a

parallel-in/serial-in, serial-out 8-bit shift register. The storage register

and shift register have separate positive edge triggered clocks. The

shift register has asynchronous reset and when SHCP is Low, it has

asynchronous load.

The shift register load function has been modified to load when both

SHLD and SHCP are Low. When SHCP is High the shift register

load operation is not performed. Data will be properly shifted on the

rising edge of SHCP when SHLD is High.

PIN CONFIGURATION

16

15

14

13

12

11

10

7

6

5

4

3

2

1

9

8

SF00366

D1

D2

D3

D4

D5

D6

D7

GND

D0

SHLD

STCP

SHCP

SHRST

TYPE

TYPICAL SUPPLY CURRENT

(TOTAL)

74F597

135MHz

42mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

PKG DWG #

16-pin plastic DIP

N74F597N

SOT38-4

16-pin plastic SO

N74F597D

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F (U.L.)

HIGH/LOW

LOAD VALUE

HIGH/LOW

Ds

Serial data input

1.0/0.033

20

µA/20µA

D0–D7

Parallel data inputs

1.0/0.033

20

µA/20µA

SHCP

Shift register clock pulse input

1.0/0.033

20

µA/20µA

STCP

Storage register clock pulse input

1.0/0.033

20

µA/20µA

SHLD

Shift register load input (active Low)

1.0/0.033

20

µA/20µA

SHRST

Shift register reset input (active Low)

1.0/0.033

20

µA/20µA

Qs

Serial data output

50/33

1.0mA/20mA

NOTE:

One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.