Philips Semiconductors

Product specification

74F74

Dual D-type flip-flop

2

1996 Mar 12

853 0335 16554

FEATURE

DESCRIPTION

The 74F74 is a dual positive edge-triggered D-type flip-flop featuring

individual data, clock, set, and reset inputs; also true and

complementary outputs. Set (SD) and reset (RD) are asynchronous

active low inputs and operate independently of the clock input. When

set and reset are inactive (high), data at the D input is transferred to

the Q and Q outputs on the low-to-high transition of the clock. Data

must be stable just one setup time prior to the low-to-high transition of

the clock for predictable operation. Clock triggering occurs at a

voltage level and is not directly related to the transition time of the

positive-going pulse. Following the hold time interval, data at the D

input may be changed without affecting the levels of the output.

PIN CONFIGURATION

14

13

12

11

10

9

8

7

6

5

4

3

2

1

GND

SD1

Q1

Q1

CP1

RD1

D1

RD0

D0

Q0

CP0

SD0

Q0

SF00045

TYPE

TYPICAL SUPPLY CURRENT (TOTAL)

74F74

125MHz

11.5mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

INDUSTRIAL RANGE

PKG. DWG. #

14-pin plastic DIP

N74F74N

I74F74N

SOT27-1

14-pin plastic SO

N74F74D

I74F74D

SOT108-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

D0, D1

Data inputs

1.0/1.0

20

µA/0.6mA

CP0, CP1

Clock inputs (active rising edge)

1.0/1.0

20

µA/0.6mA

SD0, SD1

Set inputs (active low)

1.0/3.0

20

µA/1.8mA

RD0, RD1

Reset inputs (active low)

1.0/3.0

20

µA/1.8mA

Q0, Q1, Q0, Q1

Data outputs

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the high state and 0.6mA in the low state.

LOGIC SYMBOL

Q0 Q0 Q1 Q1

56

98

GND = Pin 7

3

4

1

11

10

13

CP0

SD0

RD0

CP1

SD1

RD1

D0

D1

212

SF00046

IEC/IEEE SYMBOL

4

3

2

1

10

11

12

13

5

6

9

8

&

S

S

C1

C2

R

1D

2D

R

SF00047