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PCM4L 데이터시트(PDF) 29 Page - Renesas Technology Corp |
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PCM4L 데이터시트(HTML) 29 Page - Renesas Technology Corp |
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29 / 38 page ![]() R31DS0087EU0101 Rev.1.01 Page 29 Sep.28.21 pcm4l Datasheet 5.2 PDV Tolerance 5.2.1 Time Noise Tolerance for PTS - G.8273.4 Clause 8.3 (using G.8275.2 Profile) For test details, see the Calnex Test Guide CX3013. This test checks whether the equipment clock can maintain network limits at the output (max|TE|L < 1350ns) with maximum noise at the input. ▪ Reference Model 1 (NoBCs_HighStablility) – Network Topology with no intermediate time-aware devices ▪ Reference Model 2 (WithBCs_NormalStablility) – Network topology of three islands, or two time-aware bridging devices The High Stability PDV profiles model a packet selection characteristic per below (based on G.8271.2): ▪ Selection window = 200s ▪ Selection percentage = 0.25% fastest packets The pattern is then normalized so that the peak-to-peak pktSelected2wayTE is <1100 ns. The following figures show the TE performance at the output for the two reference models. Figure 12. Reference Model 1 (652nspp) |
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