 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
STR710FZ1T6 데이터시트(PDF) 43 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STR710FZ1T6 데이터시트(HTML) 43 Page - STMicroelectronics |
|
|
43 / 74 page  STR71xF Electrical parameters 43/74 Figure 16. RTC Crystal Oscillator and Resonator PLL Electrical Characteristics V33 = 3.0 to 3.6V, V33IOPLL = 3.0 to 3.6V, TA = -40 / 85 °C unless otherwise specified. CL CL RS DEVICE DEVICE Table 20. PLL1 Characteristics Symbol Parameter Test Conditions Value Unit Min Typ Max fPLLCLK1 PLL multiplier output clock fPLL1x 24 165 MHz fPLL1 PLL input clock FREF_RANGE = 0 1.5 3.0 MHz FREF_RANGE = 1 MX[1:0]=’00’ or ‘01’ 3.0 8.25 MHz FREF_RANGE = 1 MX[1:0]=’10’ or ‘11’ 3.0 6 MHz PLL input clock duty cycle 25 75 % fFREE1 PLL free running frequency FREF_RANGE = 0 MX[1:0]=’01’ or ‘11’ 125 kHz FREF_RANGE = 0 MX[1:0]=’00’ or ‘10’ 250 kHz FREF_RANGE = 1 MX[1:0]=’01’ or ‘11’ 250 kHz FREF_RANGE = 1 MX[1:0]=’00’ or ‘10’ 500 kHz tLOCK1 PLL lock time FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 µs FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 µs ∆tJITTER1 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
