74F85 datasheet(2/10 Pages) PHILIPS

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Philips Semiconductors

Product specification

74F85

4-bit magnitude comparator

September 27, 1994

853–0055 13903

FEATURES

• High-impedance NPN base inputs for reduced loading

(20

µA in High and Low states)

• Magnitude comparison of any binary words

• Serial or parallel expansion without extra gating

DESCRIPTION

The 74F85 is a 4-bit magnitude comparator that can be expanded to

almost any length. It compares two 4-bit binary, BCD, or other

monotonic codes and presents the three possible magnitude results

at the outputs. The 4-bit inputs are weighted (A0–A3) and (B0–B3)

where A3 and B3 are the most significant bits. The operation of the

74F85 is described in the Function Table, showing all possible logic

conditions. The upper part of the table describes the normal

operation under all conditions that will occur in a single device or in

a series expansion scheme. In the upper part of the table the three

outputs are mutually exclusive. In the lower part of the table, the

outputs reflect the feed-forward conditions that exist in the parallel

expansion scheme. The expansion inputs IA>B, and IA=B and IA<B

are the least significant bit positions. When used for series

expansion, the A>B, A=B and A<B outputs of the lease significant

word are connected to the corresponding IA>B, IA=B and IA<B inputs

of the next higher stage. Stages can be added in this manner to any

length, but a propagation delay penalty of about 15ns is added with

each additional stage. For proper operation, the expansion inputs of

the least significant word should be tied as follows: IA>B = Low,

IA=B = High, and IA<B = Low.

PIN CONFIGURATION

A<B

VCC

IA<B

A=B

IA=B

IA>B

A>B

GND

SF00075

TYPE

TYPICAL

PROPAGATION

DELAY

TYPICAL

SUPPLY CURRENT

(TOTAL)

74F85

7.0ns

40mA

ORDERING INFORMATION

DESCRIPTION

COMMERCIAL RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

PKG DWG #

16-pin plastic DIP

N74F85N

SOT38-4

16-pin plastic SO

N74F85D

SOT162-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/LOW

LOAD VALUE HIGH/LOW

A0–A3

Comparing inputs

1.0/0.033

µA/20µA

B0–B3

Comparing inputs

1.0/0.033

µA/20µA

IA<B, IA=B, IA>B

Expansion inputs (active High)

1.0/0.033

µA/20µA

A<B, A=B, A>B

Data outputs (active High)

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the High state and 0.6mA in the Low state.

LOGIC SYMBOL

VCC = Pin 16

GND = Pin 8

SF00076

A>B

A=B

A<B

IA>B

IA=B

IA<B

IEC/IEEE SYMBOL

SF00077

COMP

P<Q

P=Q

P>Q

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