EM6620WS11 datasheet(15/56 Pages) EMMICRO

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EM6620

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6.2.2 Pull-up/down

Each of the input port terminals PA[3:0] has a resistor integrated which can be used either as pull-up or pull-

down resistor, depending on the selected metal mask options. The pull resistor can be inhibited using the

NoPullPA[n] bits in the register OptNoPullPA. Refer also to chapter 16.1.1 .

Table 6.2.1. Pull-up or Pull-down Resistor on Port A select

Option mask

pull-up

MPAPU[n]

Option mask

pull-down

MPAPD[n]

NoPullPA[n]

value

Action

no pull-up, no pull-down

yes

no pull-up, pull-down

yes

no pull-up, no pull-down

yes

pull-up, no pull-down

yes

no pull-up , no pull-down

yes

not allowed*

* only pull-up or pull-down may be chosen on any port A terminal (one choice is excluding the other)

Any port A input must never be left open (high impedance state, not connected, etc. ) unless the internal pull

resistor is in place (mask option) and switched on (register selection). Any open input may draw a significant

cross current which adds to the total chip consumption.

6.2.3 Software test variables

The port A terminals PA[2:0] are also used as input conditions for conditional software branches. Independent

of the OPtDebIntPA and the OPTIntEdgPA. These CPU inputs are always debounced and non-inverted.

- debounced PA[0] is connected to CPU TestVar1

- debounced PA[1] is connected to CPU TestVar2

- debounced PA[2] is connected to CPU TestVar3

6.2.4 Port A for 10-Bit Counter and MSC

The PA[0] and PA[3] inputs can be used as the clock input terminal for the 10 bit counter in "event count"

mode. As for the IRQ generation one can choose debouncer or direct input with the register OPTDebIntPA and

non-inverted or inverted input with the register OPTIntEdgPA. Debouncer input is always recommended.

Pad input PA[3] is also used as start/stop control for the millisecond counter. This control signal is derived from

PA[3], it is independent of the port A debouncer and edge selection. Refer also to Figure 10.

6.3 Port A registers

Table 6.3.1 Register RegPA

Bit

Name

Reset

R/W

Description

PA[3]

PA[3] input status

PA[2]

PA[2] input status

PA[1]

PA[1] input status

PA[0]

PA[0] input status

* Direct read on Port A terminals

with

n=0…3

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