FXPS7115D4S datasheet(17/74 Pages) NXP

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NXP Semiconductors

FXPS7115D4S

Digital absolute pressure sensor, 40 kPa to 115 kPa

7.4.7 I2C timing diagram

aaa-029751

SDA

70 %

30 %

70 %

30 %

70 %

30 %

70 %

9th clock

... cont.

tHIGH

tLOW

tVD;DAT

tBUF

tHD;DAT

tHD;STA

1 / fSCL

1st clock cycle

tSU;DAT

tSU;STO

tVD;ACK

tHD;STA

tSU;STA

tSP

30 %

70 %

30 %

70 %

30 %

70 %

30 %

SCL

... SDA

... SCL

Figure 19. I2C timing diagram

7.5 Standard 32-bit SPI protocol

The device includes a standard SPI protocol requiring 32-bit data packets. The device

is a client device and requires a low base clock value (CPOL = 0) with data captured

on the rising edge of the clock and data propagated on the falling edge of the clock

(CPHA = 0). The most significant bit is transferred first (MSB first). SPI transfers are

completed through a sequence of two phases. During the first phase, the command is

transmitted from the SPI host to the device. During the second phase, response data is

transmitted from the client device. MOSI and SCLK transitions are ignored when SS_B is

not asserted.

FXPS7115D4S

All information provided in this document is subject to legal disclaimers.

Objective data sheet

Rev. 1 — 9 August 2022

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