December 1990

2

Philips Semiconductors

Product specification

Presettable synchronous 4-bit binary

counter; synchronous reset

74HC/HCT163

FEATURES

• Synchronous counting and loading

• Two count enable inputs for n-bit cascading

• Positive-edge triggered clock

• Synchronous reset

• Output capability: standard

GENERAL DESCRIPTION

The 74HC/HCT163 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT163 are synchronous presettable binary

counters which feature an internal look-ahead carry and

can be used for high-speed counting.

Synchronous operation is provided by having all flip-flops

clocked simultaneously on the positive-going edge of the

clock (CP).

HIGH or LOW level. A LOW level at the parallel enable

input (PE) disables the counting action and causes the

counter on the positive-going edge of the clock (providing

that the set-up and hold time requirements for PE are met).

Preset takes place regardless of the levels at count enable

inputs (CEP and CET).

For the “163” the clear function is synchronous.

A LOW level at the master reset input (MR) sets all four

next positive-going transition on the clock (CP) input

(provided that the set-up and hold time requirements for

MR are met). This action occurs regardless of the levels at

PE, CET and CEP inputs.

This synchronous reset feature enables the designer to

modify the maximum count with only one external NAND

gate.

The look-ahead carry simplifies serial cascading of the

counters. Both count enable inputs (CEP and CET) must

be HIGH to count. The CET input is fed forward to enable

the terminal count output (TC). The TC output thus

enabled will produce a HIGH output pulse of a duration

pulse can be used to enable the next cascaded stage.

The maximum clock frequency for the cascaded counters

is determined by the CP to TC propagation delay and CEP

to CP set-up time, according to the following formula:

1

t

P max

t

+

-------------------------------------------------------------------------------------------------

=

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

propagation delay

CP to TC

CET to TC

17

21

11

20

25

14

ns

ns

ns

maximum clock frequency

51

50

MHz

input capacitance

3.5

3.5

pF

power dissipation

capacitance per package

notes 1 and 2

33

35

pF

Notes

dynamic power dissipation

where:

outputs

pF

2. For HC the condition is

For HCT the condition is