PIC16F15213 datasheet(20/439 Pages) MICROCHIP

20 / 439 page

Enhanced Mid-Range CPU

This family of devices contains an enhanced mid-range 8-bit CPU core. The CPU has 50 instructions. Interrupt

capability includes automatic context saving. The hardware stack is 16-level deep and has overflow and underflow

Reset capability. Direct, Indirect, and Relative Addressing modes are available. Two File Select Registers (FSR)

provide the ability to read program and data memory.

Figure 7-1. Core Data Path Diagram

Filename:

Core Data Path Diagram=GUID-70F1F30C-1B2B-4155-96C9-1E02D094618D=1=en-US=Source.vsdx

Title:

Last Edit:

12/19/2019

First Used:

Notes:

Address Latch

Program Memory

Data Latch

PCLATH

PCL

16-Level Stack

STKPTR

Data Latch

Data Memory

Address Latch

Data Address

FSR0

FSR1

inc/dec

logic

BSR

Address

Decode

Program Counter

Instruction

Latch

Instruction

Decode and

Control

ALU

Instruction Bus

State Machine

Control Signals

Data Bus

STATUS

W Register

MUX

7.1

Automatic Interrupt Context Saving

During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the

interrupt. This saves stack space and user code.

PIC16F15213/14/23/24/43/44

Enhanced Mid-Range CPU

and its subsidiaries

Data Sheet

DS40002195E-page 20

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