UPSD325X datasheet(132/176 Pages) STMICROELECTRONICS

부품명	UPSD325X

상세설명	Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM

PDF	176 Pages

Scroll/Zoom	100%

제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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132 / 176 page

µPSD325X DEVICES

132/176

Ports A and B – Functionality and Structure

Ports A and B have similar functionality and struc-

ture, as shown in Figure 65. The two ports can be

configured to perform one or more of the following

functions:

MCU I/O Mode

CPLD Output – Macrocells McellAB7-McellAB0

can be connected to Port A or Port B. McellBC7-

McellBC0 can be connected to Port B or Port C.

CPLD Input – Via the Input Macrocells (IMC).

Latched Address output – Provide latched

address output as per Table 94.

Open Drain/Slew Rate – pins PA3-PA0 and

PB3-PB0 can be configured to fast slew rate,

pins PA7-PA4 and PB7-PB4 can be configured

to Open Drain Mode.

Peripheral Mode – Port A only (80-pin package)

Figure 65. Port A and Port B Structure

DATA OUT

REG.

ADDRESS

MACROCELL OUTPUTS

ENABLE PRODUCT TERM (.OE)

ALE

READ MUX

CPLD - INPUT

CONTROL REG.

DIR REG.

INPUT

MACROCELL

ENABLE OUT

DATA IN

OUTPUT

SELECT

OUTPUT

MUX

PORT

A OR B PIN

DATA OUT

ADDRESS

A[ 7:0]

AI06605

UPSD325X 데이터시트(PDF) 132 Page - STMicroelectronics

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