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UPSD325X 데이터시트(PDF) 157 Page - STMicroelectronics

부품명 UPSD325X
상세설명  Flash Programmable System Devices with 8032 Microcontroller Core and 256Kbit SRAM
PDF  176 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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UPSD325X 데이터시트(HTML) 157 Page - STMicroelectronics

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µPSD325X DEVICES
Figure 78. Input to Output Disable / Enable
Table 121. CPLD Combinatorial Timing (5V Devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
Table 122. CPLD Combinatorial Timing (3V Devices)
Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount
2. tPD for MCU address and control signals refers to delay from pins on Port 0, Port 2, RD WR, PSEN and ALE to CPLD combinatorial
output (80-pin package only)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate1
Unit
tPD
2
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
20
+ 2
+ 10
– 2
ns
tEA
CPLD Input to CPLD Output
Enable
21
+ 10
– 2
ns
tER
CPLD Input to CPLD Output
Disable
21
+ 10
– 2
ns
tARP
CPLD Register Clear or Preset
Delay
21
+ 10
– 2
ns
tARPW
CPLD Register Clear or Preset
Pulse Width
10
+ 10
ns
tARD
CPLD Array Delay
Any
macrocell
11
+ 2
ns
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
Off
Slew
rate1
Unit
tPD
2
CPLD Input Pin/Feedback to
CPLD Combinatorial Output
40
+ 4
+ 20
– 6
ns
tEA
CPLD Input to CPLD Output
Enable
43
+ 20
– 6
ns
tER
CPLD Input to CPLD Output
Disable
43
+ 20
– 6
ns
tARP
CPLD Register Clear or
Preset Delay
40
+ 20
– 6
ns
tARPW
CPLD Register Clear or
Preset Pulse Width
25
+ 20
ns
tARD
CPLD Array Delay
Any
macrocell
25
+ 4
ns
tER
tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863



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