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UPSD325X 데이터시트(PDF) 161 Page - STMicroelectronics |
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UPSD325X 데이터시트(HTML) 161 Page - STMicroelectronics |
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161 / 176 page ![]() 161/176 µPSD325X DEVICES Table 126. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices) Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew Rate Unit fMAXA Maximum Frequency External Feedback 1/(tSA+tCOA) 21.7 MHz Maximum Frequency Internal Feedback (fCNTA) 1/(tSA+tCOA–10) 27.8 MHz Maximum Frequency Pipelined Data 1/(tCHA+tCLA) 33.3 MHz tSA Input Setup Time 10 + 4 + 20 ns tHA Input Hold Time 12 ns tCHA Clock High Time 17 + 20 ns tCLA Clock Low Time 13 + 20 ns tCOA Clock to Output Delay 36 + 20 – 6 ns tARD CPLD Array Delay Any macrocell 25 + 4 ns tMINA Minimum Clock Period 1/fCNTA 36 ns |
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