M5M29KB/T331AVP

Renesas LSIs

Rev.1.0_48a_bezz

17

33,554,432-BIT (4,194,304-WORD BY 8-BIT /2,097,152-WORD BY 16-BIT)

CMOS 3.3V-ONLY, BLOCK ERASE FLASH MEMORY

During power up / down, by the noise pulses on control pins, the device has possibility of accidental erase of programming.

The device must be protected against initiation of write cycle for memory contents during power up / down. The delay time

of min. 2 µsec is always required before read operation or write operation is initiated from the time Flash VCC reaches

Flash VCC min. during power up /down. By holding RP#=VIL, the contents of memory is protected during Flash VCC

power up / down. During power up, RP# must be held VIL for min. 2µs from the time Flash VCC reaches Flash VCC min..

During power down, RP# must be held VIL until Flash VCC reaches GND. RP# doesn’t have latch mode, therefore RP#

must be held VIH during read operation or erase / program operation.

Parameter

Min.

Typ.

Max.

Units

Block Erase Time

150

600

ms

Main Block Write Time (Byte Mode)

2

8

sec

Main Block Write Time (Word Mode)

1

4

sec

Page Write Time

4

80

ms

Flash to Page Buffer Time

100

150

µs

Parameter

Min.

Typ.

Max.

Unit

Program Susupend Time

15

µs

Erase Susupend Time

15

µs

symbol

Parameter

Min.

Typ.

Max.

Unit

tVCS

RP#=VIH Setup Time from Flash VCC min.

2

µs

Flash VCC Power Up / Down Timing

Program Suspend / Erase Suspend Time

Program / Erase Time