ATMEGA6450SLASHV datasheet(39/347 Pages) ATMEL

39 / 347 page

ATmega325/3250/645/6450

2570A–AVR–09/04

Figure 15. Reset Logic

Notes:

1. The Power-on Reset will not work unless the supply voltage has been below VPOT

(falling)

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-

tion level is defined in Table 16. The POR is activated whenever V

CC is below the

detection level. The POR circuit can be used to trigger the start-up Reset, as well as to

detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-

ing the Power-on Reset threshold voltage invokes the delay counter, which determines

how long the device is kept in RESET after V

CC rise. The RESET signal is activated

again, without any delay, when V

CC decreases below the detection level.

Table 16. Reset Characteristics

Symbol

Parameter

Condition

Min

Typ

Max

Units

VPOT

Power-on Reset Threshold

Voltage (rising)

A = -40°C

to 85°C

0.7

1.0

1.4

Power-on Reset Threshold

Voltage (falling)(1)

TA = -40°C

to 85°C

0.6

0.9

1.3

VRST

RESET Pin Threshold Voltage

VCC = 3V

0.2VCC

0.85VCC

tRST

Minimum pulse width on

RESET Pin

VCC = 3V

800

MCU Status

Brown-out

Reset Circuit

BODLEVEL [1..0]

Delay Counters

CKSEL[3:0]

TIMEOUT

DATA BUS

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

JTAG Reset

Watchdog

Oscillator

SUT[1:0]

Power-on Reset

Circuit

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