Data Sheet

LT3073

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Rev 0.

24 of 37

APPLICATIONS INFORMATION

The LT3073 is a low voltage, ultra-low noise, and ultra-fast transient response linear regulator. The device supplies

up to 3A with a typical dropout voltage of 45mV. A 4.7µF reference bypass capacitor decreases output voltage noise

to 1.2μVRMS. The LDO’s wide bandwidth and high PSRR permit the use of small ceramic capacitors, saving bulk

capacitance and cost. The LT3073 is ideal for high-performance FPGAs, microprocessors, RF communication, and

noise-sensitive supply applications.

Output Voltage

The LT3073’s unity-gain operation provides virtually constant output noise, PSRR, bandwidth, and load regulation

independent of the programmed output voltage. Output voltages are digitally selectable in 50mV increments from

0.5V to 1.2V; 100mV increments from 1.2V to 1.8V; and discrete levels at 2V, 2.5V, 3V, 3.3V, and 4.2V.

Three tri-level input pins, VO0, VO1, and VO2, select the output voltage. Table 6 illustrates the three-bit digital word-to-

output voltage relationship resulting from setting these pins high, low, or allowing them to float. An input logic low

state is guaranteed with less than 300mV referenced to GND, and a logic high state is guaranteed with greater than

1.97V. The range between 950mV to 1.15V defines the logic Hi-Z (input floating) state. These pins may be connected

high by strapping them to VBIAS or driving them with digital ports. Pins that float may either float or require logic that

has Hi-Z output capability. This allows the output voltage to be dynamically changed if necessary.

Table 6. VOUT Selection Matrix

0 = Low, Z = Hi-Z (Float), 1 = High