L

0.47

H

m

MODE/SYNC

SW

FB

VIN

V

IN

2.75 V -

V

6

C

IN

22 mF

C

OUT

47

F

m

TPS62810-Q1

EN

R

1

V

OUT

R

2

GND

PG

SS/TR

COMP/FSET

C

SS

R

3

C

FF

f

EXT

Figure 10-60. Schematic Using External Synchronization

VIN = 5 V

RCF = 8.06 kΩ

IOUT = 0.1 A

VOUT = 1.8 V

fEXT = 2.5 MHz

Figure 10-61. Switching from External

Synchronization to Power-Save Mode (PFM)

VIN = 5 V

RCF = 8.06 kΩ

IOUT = 1 A

VOUT = 1.8 V

fEXT = 2.5 MHz

Figure 10-62. Switching from External

Synchronization to Internal Fixed Frequency

10.4 Power Supply Recommendations

The TPS6281x-Q1 device family has no special requirements for its input power supply. The output current of

the input power supply must be rated according to the supply voltage, output voltage, and output current of the

TPS6281x-Q1.

10.5 Layout

10.5.1 Layout Guidelines

A proper layout is critical for the operation of a switched mode power supply, even more at high switching

frequencies. Therefore, the PCB layout of the TPS6281x-Q1 demands careful attention to ensure operation and

to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load),

stability and accuracy weaknesses increased EMI radiation and noise sensitivity.

See Layout Example for the recommended layout of the TPS6281x-Q1, which is designed for common external

ground connections. The input capacitor must be placed as close as possible between the VIN and GND pin.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched load

current must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) for

wires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the IC

TPS62810-Q1, TPS62811-Q1, TPS62812-Q1, TPS62813-Q1

SLVSDU1J – AUGUST 2018 – REVISED MARCH 2023

www.ti.com

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