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M95128-DF 데이터시트(PDF) 26 Page - STMicroelectronics

부품명 M95128-DF
상세설명  128-Kbit serial SPI bus EEPROM with high-speed clock
PDF  48 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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M95128-DF 데이터시트(HTML) 26 Page - STMicroelectronics

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Table 13. Cycling performance by groups of four bytes
Symbol
Parameter
Test condition
Min.
Max.
Unit
Ncycle
Write cycle endurance(1)
TA ≤ 25 °C, VCC(min) < VCC < VCC(max)
-
4,000,000
Write cycle(2)
TA = 85 °C, VCC(min) < VCC < VCC(max)
-
1,200,000
1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where
N is an integer. The Write cycle endurance is defined by characterization and qualification.
2. A Write cycle is executed when either a Page write, a Byte write, a WRSR, a WRID or an LID instruction is decoded. When
using the Byte write, the Page write or the WRID instruction, refer also to Section 6.6.1 Cycling with error correction code
(ECC x4).
Table 14. Memory cell data retention
Parameter
Test condition
Min.
Unit
Data retention(1)
TA = 55 °C
200
Year
1. The data retention behaviour is checked in production, while the 200-year limit is defined from characterization and
qualification results.
Table 15. Capacitance
Symbol
Parameter
Test condition(1)
Min.
Max.
Unit
COUT
Output capacitance (Q)
VOUT = 0 V
-
8
pF
CIN
Input capacitance (D)
VIN = 0 V
-
8
pF
Input capacitance (other pins)
VIN = 0 V
-
6
pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz
M95128-W M95128-R M95128-DF
DC and AC parameters
DS1356 - Rev 20
page 26/48



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