| 전자부품 데이터시트 검색엔진 |
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LP3905 데이터시트(PDF) 7 Page - National Semiconductor (TI) |
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LP3905 데이터시트(HTML) 7 Page - National Semiconductor (TI) |
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7 / 15 page ![]() Typical Application Circuit Functional Description POWER UP/DOWN PROCEDURE The LP3905 Bucks and LDOs are powered UP/DOWN with 2 control pins, EN1 and EN2. In order for the enable pins to operate, V IN1 and VIN2 should be set to a voltage level higher than V UVLO_R (specified in electrical characteristic). Once enabled, EN1 will turn on Buck1, LDO1 and LDO2. EN2 can independently be used to enable Buck2. Figure 6 illustrates the power UP/DOWN timing sequence of the LP3905 blocks for V EN ≥ V IH (min) (enable) and VEN ≤V IL (max) (disable). Both linear regulators have active pulldowns when the out- puts are disabled. 20152911 FIGURE 5. Typical Application Circuit For Adjustable Device 20152904 EN1 and EN2 can be controlled fully independently. LDOs will be turned on only after Buck1 is powered up. LDOs are powered on simultaneously. In case EN1 and EN2 are enabled at the same time, power up of Buck2 is delayed by 50µs in order to minimize the inrush current from the battery. When EN1 and EN2 are disabled, the relevant output voltages are turned off. FIGURE 6. LP3905 Power UP/DOWN Timing Sequence www.national.com 7 |
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