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STM32F103C8T7TR 데이터시트(PDF) 76 Page - STMicroelectronics

부품명 STM32F103C8T7TR
상세설명  Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces
PDF  116 Pages
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STM32F103C8T7TR 데이터시트(HTML) 76 Page - STMicroelectronics

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Electrical characteristics
STM32F103x8, STM32F103xB
76/116
DS5319 Rev 18
Figure 37. ADC accuracy characteristics
Table 49. ADC accuracy(1) (2) (3)
1. ADC DC accuracy values are measured after internal calibration.
2. Better performance can be achieved in restricted VDD, frequency and temperature ranges.
3. Injecting a negative current on any analog input pins should be avoided as this significantly reduces the
accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky
diode (pin to ground) to standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
Symbol
Parameter
Test conditions
Typ
Max(4)
4. Evaluated by characterization, not tested in production, unless otherwise specified.
Unit
ET
Total unadjusted error
fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 kΩ,
VDDA = 2.4 V to 3.6 V
Measurements made after
ADC calibration
±2
±5
LSB
EO
Offset error
±1.5
±2.5
EG
Gain error
±1.5
±3
ED
Differential linearity error
±1
±2
EL
Integral linearity error
±1.5
±3
MSv19880V6
(1) Example of an actual transfer curve
(2) Ideal transfer curve
(3) End-point correlation line
n = ADC resolution
ET = total unadjusted error: maximum deviation
between the actual and ideal transfer curves
EO = offset error: maximum deviation between the first
actual transition and the first ideal one
EG = gain error: deviation between the last ideal
transition and the last actual one
ED = differential linearity error: maximum deviation
between actual steps and the ideal one
EL = integral linearity error: maximum deviation between
any actual transition and the end point correlation line
2
n-1
7
6
5
4
3
2
1
0
Output code
EO
VSSA
2
n-2
2
n-3
VREF+ (VDDA)
ET
EL
ED
1 LSB ideal
EG
(1)
(2)
(3)
(or
)]
[1LSB =
VDDA
2
n
VREF+
2
n



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