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MM54HC73J 데이터시트(PDF) 1 Page - National Semiconductor (TI) |
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MM54HC73J 데이터시트(HTML) 1 Page - National Semiconductor (TI) |
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1 / 6 page ![]() TLF5072 January 1988 MM54HC73MM74HC73 Dual J-K Flip-Flops with Clear General Description These J-K Flip-Flops utilize advanced silicon-gate CMOS technology They possess the high noise immunity and low power dissipation of standard CMOS integrated circuits These devices can drive 10 LS-TTL loads These flip-flops are edge sensitive to the clock input and change state on the negative going transition of the clock pulse Each one has independent J K CLOCK and CLEAR inputs and Q and Q outputs CLEAR is independent of the clock and accomplished by a low level on the input The 54HC74HC logic family is functionally as well as pin- out compatible with the standard 54LS74LS logic family All inputs are protected from damage due to static dis- charge by internal diode clamps to VCC and ground Features Y Typical propagation delay 16 ns Y Wide operating voltage range 2 – 6V Y Low input current 1 mA maximum Y Low quiescent current 40 mA (74HC Series) Y High output drive 10 LS-TTL loads Connection and Logic Diagrams Dual-In-Line Package Top View TLF5072 – 1 Order Number MM54HC73 or MM74HC73 Truth Table Inputs Outputs CLR CLK J K Q Q LX X X L H H v L L Q0 Q0 H v HL H L H v LH L H H v H H TOGGLE H H X X Q0 Q0 TLF5072 – 2 (1 of 2) TLF5072 – 3 C1995 National Semiconductor Corporation RRD-B30M115Printed in U S A |
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