OV7750 datasheet(21/125 Pages) OMNIVISION

21 / 125 page

10.12.2015

PRODUCT SPECIFICATION

proprietary to OmniVision Technologies

2-5

2.3.2 VSYNC timing in MIPI mode

The VSYNC rising edge delay is controlled by register vsync_delay ({0x4314, 0x4315, 0x4316}) in all three VSYNC

modes. VSYNC width is controlled by register vsync_width_pixel ({0x4311, 0x4312}) for VSYNC modes 1 and 2. The

steps of both registers vsync_delay and vsync_width_pixel are 1 system clock cycle.

Note that VSYNC timing in mode 3 is a long VSYNC mode. The register vsync_width_pixel ({0x4311, 0x4312}) controls

VSYNC falling edge differently.

2.3.2.1 VSYNC mode 1

In mode 1, VSYNC is generated by the internal start of frame (SOF) signal (see

figure 2-4).

figure 2-4

VSYNC timing in mode 1

2.3.2.2 VSYNC mode 2

In mode 2, VSYNC is generated by the internal end of frame (EOF) signal (see

figure 2-5).

figure 2-5

VSYNC timing in mode 2

2.3.2.3 VSYNC mode 3

In mode 3, VSYNC is generated by EOF and SOF (see

figure 2-6).

figure 2-6

VSYNC timing in mode 3

pclk

VSYNC

SOF

can be adjusted

7750_DS_2_4

pclk

EOF

VSYNC

can be adjusted

7750_DS_2_5

pclk

EOF

VSYNC

SOF

can be adjusted

7750_DS_2_6

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