| 전자부품 데이터시트 검색엔진 |
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EFP01 데이터시트(PDF) 96 Page - Silicon Laboratories |
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EFP01 데이터시트(HTML) 96 Page - Silicon Laboratories |
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96 / 158 page ![]() 6.2.3 STATUS_GM Offset Bit Position 0x02 7 6 5 4 3 2 1 0 Reset 0 0 0 0 0 0 0 1 Access Name Table 6.3. STATUS_GM Bit Name Reset Access Description 7 VDD_LOW_UNMASK 0 read-write Set to unmask VDD Low status flag in the STATUS_G register. 6 CCC_ISDONE_UNMASK 0 read-write Set to unmask Coulomb Counting Calibration status flag in the STATUS_G register. 5 CC_FULL_UNMASK 0 read-write Set to unmask Coulomb Counting over Threshold status flag in the STATUS_G register. 4 VOLT_FAULT_UNMASK 0 read-write Set to unmask Voltage Fault status flag in the STATUS_G register. 3 TEMP_FAULT_UNMASK 0 read-write Set to unmask Temperature Fault status flag in the STA- TUS_G register. 2 I2C_FAULT_UNMASK 0 read-write Set to unmask I2C Fault status flag in the STATUS_G reg- ister. 1 OTP_CRC_FAULT_UN- MASK 0 read-write Set to unmask OTP CRC violation status flag in the STA- TUS_G register. 0 OTP_READ_UNMASK 1 read-write Set to unmask OTP Read status flag in the STATUS_G register. This bit is set by default - therefore, every power-up and reset deassertion (which causes an OTP read), results in an unmasked flag and the IRQ pin assertion. It is recommended to keep this flag unmasked always to ensure that any EFP01 reset will result in an IRQ to the host MCU, allowing the host MCU to reinitialize any EFP01 registers. EFP01 Energy Friendly PMIC Family Data Sheet Register Definitions silabs.com | Building a more connected world. Rev. 1.3 | 96 |
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