HC705RC16GRSSLASHD datasheet(33/120 Pages) NXP

33 / 120 page

Central Processor Unit

Condition Code Register

MC68HC705RC16 — Rev. 3.0

General Release Specification

Central Processor Unit

3.5 Condition Code Register

The condition code register (CCR) is a 5-bit register in which four bits are

used to indicate the results of the instruction just executed, and the fifth

bit indicates whether interrupts are masked. These bits can be tested

individually by a program, and specific actions can be taken as a result

of their state. Each bit is explained in the following paragraphs.

H — Half Carry

This bit is set during ADD and ADC operations to indicate that a carry

occurred between bits 3 and 4.

I — Interrupt

When this bit is set, timer and external interrupts are masked

(disabled). If an interrupt occurs while this bit is set, the interrupt is

latched and processed as soon as the interrupt bit is cleared.

N — Negative

When set, this bit indicates that the result of the last arithmetic, logical,

or data manipulation was negative.

Z — Zero

When set, this bit indicates that the result of the last arithmetic, logical,

or data manipulation was zero.

C — Carry/Borrow

When set, this bit indicates that a carry or borrow out of the arithmetic

logical unit (ALU) occurred during the last arithmetic operation. This

bit is also affected during bit test and branch instructions and during

shifts and rotates.

CCR

HIN

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705RC16GRS/D 데이터시트(PDF) 33 Page - NXP Semiconductors