22

AT49LL080

3273C–FLASH–5/03

Notes:

1. Minimum and maximum times have different loads. See PCI spec.

2. For purposes of Active/Float timing measurements, the high-Z or “off” state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

3. This parameter applies to any input type (excluding CLK).

Output Timing Parameters

Input Timing Parameters

Signal Timing Parameters

Symbol

PCI Symbol

Parameter

Min

Max

Units

t

CHQX

t

val

CLK to Data Out

(1)

211

ns

CLK to Active (Float to Active Delay)

(2)

2ns

t

CHQZ

t

off

CLK to Inactive (Active to Float Delay)

(2)

28

ns

t

AVCH

t

su

Input Set-up Time

(3)

9

ns

t

CHAX

t

CHDX

t

h

Input Hold Time

(3)

0

ns

Reset Active Time after Power Stable

1

ms

t

CSPL

t

rst-clk

Reset Active Time after CLK Stable

100

µs

t

PLQZ

t

rst-off

Reset Active to Output Float Delay

(2)

48

ns

CLK

LAD[3:0]

(Valid Output Data)

LAD[3:0]

(Float Output Data)

CLK

LAD[3:0]

(Valid Input Data)

Inputs Valid