HC805P18GRSSLASHD datasheet(32/111 Pages) NXP

32 / 111 page

GENERAL RELEASE SPECIFICATION

INTERRUPTS

Rev. 1.0

Any enabled IRQ interrupt source sets the IRQ latch on the falling edge of the

IRQ pin or a port A pin if port A interrupts have been enabled. If edge-only

sensitivity is chosen by a mask option, only the IRQ latch output can activate a

request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ

interrupt sensitive to the following cases:

Falling edge on the IRQ pin with all enabled port A interrupt pins at a high

level.

Falling edge on any enabled port A interrupt pin with all other enabled

port A interrupt pins and the IRQ pin at a high level.

If level sensitivity is chosen, the active high state of the IRQ input can also

activate an IRQ request to the CPU to generate the IRQ interrupt sequence.

This makes the IRQ interrupt sensitive to the following cases:

Low level on the IRQ pin

Falling edge on the IRQ pin with all enabled port A interrupt pins at a high

level

Low level on any enabled port A interrupt pin

Falling edge on any enabled port A interrupt pin with all enabled port A

interrupt pins and the IRQ pin at a high level

This interrupt is serviced by the interrupt service routine located at the address

specified by the contents of $3FFA and $3FFB. The IRQ latch is automatically

cleared by entering the interrupt service routine.

Optional External Interrupts (PA0–PA7)

The IRQ interrupt can be triggered by the inputs on the PA0 through PA7 port

pins if enabled by individual mask options. With pullup enabled, each port A pin

can activate the IRQ interrupt function and the interrupt operation will be the

same as for inputs to the IRQ pin. Once enabled by mask option, each individual

port A pin can be disabled as an interrupt source if its corresponding DDR bit is

configured for output mode.

NOTE

The BIH and BIL instructions apply to the output of the logic OR

function of the enabled PA0 through PA7 interrupt pins and the IRQ

pin. The BIH and BIL instructions do not test only the state of the IRQ

pin.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC805P18GRS/D 데이터시트(PDF) 32 Page - NXP Semiconductors