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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HC805K3GRS/D 데이터시트(PDF) 41 Page - NXP Semiconductors |
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HC805K3GRS/D 데이터시트(HTML) 41 Page - NXP Semiconductors |
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41 / 119 page  General Release Specification CPU Interrupt Processing MC68HC805K3 — Rev. 1.0 Interrupts 41 An RTI instruction is used to signify when the interrupt software service routine is complete. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume at the next instruction that was to be executed when the interrupt took place. Figure 4-1 shows the sequence of events that occurs during interrupt processing. Figure 4-2 shows the stacking and unstacking order into the RAM that is associated with an interrupt service routine. Figure 4-1. Interrupt Processing Flowchart FROM RESET IS I BIT SET? LOAD PC FROM: SWI: $03FC, $03FD IRQ: $03FA-$03FB TIMER: $03F8-$03F9 SET I BIT IN CCR STACK PCL, PCH, X, A, CC CLEAR IRQ REQUEST LATCH RESTORE REGISTERS FROM STACK CC, A, X, PCH, PCL Y N IRQ EXTERNAL INTERRUPT? Y N TIMER INTERNAL INTERRUPT? Y N EXECUTE INSTRUCTION FETCH NEXT INSTRUCTION RTI INSTRUCTION ? Y N SWI INSTRUCTION ? Y N Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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