74LVC169DB datasheet(9/14 Pages) PHILIPS

9 / 14 page

Philips Semiconductors

Product specification

74LVC169

Presettable synchronous 4-bit up/down

binary counter

1998 May 20

AC WAVEFORMS

VM = 1.5 V at VCC w 2.7 V

VM = 0.5 S VCC at VCC < 2.7 V

VOL and VOH are the typical output voltage drop that occur with the output load.

1/fMAX

tPLH

tPHL

CP INPUT

Qn, TC OUTPUT

SY00071

GND

VOH

VOL

Waveform 1.

Clock (CP) to outputs (Qn, TC) propagation

delays, the clock pulse width and the maximum clock

frequency.

tPLH

tPHL

CET

SF00792

Waveform 2.

Input (CET) to output (TC) propagation delays

and output transition times.

tPLH

tPHL

U/D

SF00793

Waveform 3.

Master reset (MR) pulse width, the master reset

to output (Qn, TC) propagation delays and the master reset to

clock (CP) removal times.

The shaded areas indicate when the input is permitted

to change for predictable output performance.

GND

PE INPUT

CP INPUT

Dn INPUT

tSU

SC00137

Waveform 4.

Setup and hold times for the input (Dn) and

parallel enable input (PE).

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

tsu

SC00138

GND

CEP, CET

INPUT

CP INPUT

Waveform 5.

CEP and CET setup and hold times.

TEST CIRCUIT

SWITCH POSITION

PULSE

GENERATOR

D.U.T.

VCC

500

Ω

Open

GND

VCC

< 2.7V

VCC

TEST

tPLH/tPHL

Open

2.7V

2.7–3.6V

50pF

500

Ω

2 * VCC

SV00903

Waveform 6.

Load circuitry for switching times.

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