M5CAARCH-RMSLASHD datasheet(112/114 Pages) NXP

112 / 114 page

112

INDEX

C3EN

Electrical 71

Executive Processor Timing 87

Fabric Processor Timing 92

Gigabit GMII Ethernet, TBI and MII Interface Timing

Specification 83

Low Speed Serial Interface Timing 90

MDIO Serial Interface Timing 89

Mechanical 103

OC-12 Timing 86

OC-3 Timing 85

PCI Timing 87

PROM Interface Timing 91

QMU Timing 98

TLU Timing 96

XP Timing 87

System Clock Timing Description 80

System Clock Timing Diagram 80

System Interfaces

Executive Processor 23

Table Lookup Unit 25

Test Signals 57

Test Signals, Miscellaneous, For JTAG, Scan, and Internal Test

Routines 57

Timing Outline

PROM Interface 47

TLU Signal Groups 97

TLU SRAM Interface Signals 53

TLU Timing Description 96

TLU Timing Diagram 96

TLU Timing Specifications 96

Transceiver Interface Configuration

SONET OC-12 41

SONET OC-3 40

Transmit and Receive Pin Combinations for Gigabit Ethernet and

FibreChannel 36

Utopia2/Utopia3 ATM Mode, C-3e Network Processor to Fabric

Interface Pin Mapping 50

Utopia2/Utopia3 PHY Mode, C-3e Network Processor to Fabric

Interface Pin Mapping 50

XP Timing Specifications 87

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

M5CAARCH-RM/D 데이터시트(PDF) 112 Page - NXP Semiconductors

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