LVC2373APWDH datasheet(2/12 Pages) PHILIPS

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Philips Semiconductors

Product specification

74LVC2373A

74LVCH2373A

Octal D-type transparent latch with 5-volt tolerant

inputs/outputs; damping resistor (3-State)

1997 Mar 12

853–1940 17843

FEATURES

• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

• Supply voltage range of 2.7V to 3.6V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• Direct interface with TTL levels

• High impedance when V

CC = 0V

• Bushold on all data inputs (74LVCH2373A only)

• Integrated 30W damping resistor

DESCRIPTION

The 74LVC2373A/74LVCH2373A is a high performance, low-power,

low-voltage Si-gate CMOS device and superior to most advanced

CMOS compatible TTL families. Inputs can be driven from either

3.3V or 5V devices. This feature allows the use of these devices as

translators in a mixed 3.3V/5V environment.

The 74LVC2373A/74LVCH2373A is an octal D-type transparent

latch featuring separate D-type inputs for each latch and 3-State

outputs for bus oriented applications. A latch enable (LE) input and

an output enable (OE) input are common to all internal latches.

The ‘2373’ consists of eight D-type transparent latches with 3-State

true outputs. When LE is HIGH, data at the Dn inputs enters the

latches. In this condition the latches are transparent, i.e., a latch

output will change each time its corresponding D-input changes.

When LE is LOW the latches store the information that was present

at the D-inputs a set-up time preceding the HIGH-to-LOW transition

of LE. When OE is LOW, the contents of the eight latches are

available at the outputs. When OE is HIGH, the outputs go to the

high impedance OFF-state. Operation of the OE input does not

affect the state of the latches.

QUICK REFERENCE DATA

GND = 0V; Tamb = 25°C; tr = tf v2.5 ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

Propagation delay

Dn to Qn

LE to Qn

CL = 50pF

VCC = 3.3V

4.4

5.0

Input capacitance

5.0

CPD

Power dissipation capacitance per latch

Notes 1, 2

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW)

PD = CPD × VCC2 × fi )Σ (CL × VCC2 × fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

Σ (CL × VCC2 × fo) = sum of the outputs.

2. The condition is VI = GND to VCC.

ORDERING AND PACKAGE INFORMATION

PACKAGES

TEMPERATURE RANGE

OUTSIDE NORTH

AMERICA

NORTH AMERICA

PKG. DWG. #

20-Pin Plastic SO

–40

°C to +85°C

74LVC2373A D

SOT163-1

20-Pin Plastic SSOP Type II

–40

°C to +85°C

74LVC2373A DB

SOT339-1

20-Pin Plastic TSSOP Type I

–40

°C to +85°C

74LVC2373A PW

LVC2373APW DH

SOT360-1

20-Pin Plastic SO

–40

°C to +85°C

74LVCH2373A D

SOT163-1

20-Pin Plastic SSOP Type II

–40

°C to +85°C

74LVCH2373A DB

7LVCH2373A DB

SOT339-1

20-Pin Plastic TSSOP Type I

–40

°C to +85°C

74LVCH2373A PW

VCH2373APW DH

SOT360-1

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