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8P34S2108NLGI 데이터시트(PDF) 2 Page - Renesas Technology Corp |
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8P34S2108NLGI 데이터시트(HTML) 2 Page - Renesas Technology Corp |
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2 / 22 page ![]() 2 ©2016-2023 Renesas Electronics Corporation March 21, 2023 8P34S2108 Datasheet Pin Assignments Figure 1. Pin Assignments for 7 × 7 mm 48-VFQFPN Package – Top View Pin Descriptions Table 1. Pin Descriptions[a] Number Name Type Description 1 GND Power Power supply ground. 2 SELAB Input [PD/PU] Control input. Output amplitude select for channel B. 3 CLKB Input [PD] Non-inverting differential clock/data input for channel B. 4 nCLKB Input [PD/PU] Inverting differential clock/data input for channel B. 5 VREFB Output Bias voltage reference for the CLKB, nCLKB input pairs. 6 VDDB Power Power supply pins for the core and inputs of channel B. 7 VDDA Power Power supply pins for the core and inputs of channel A. 8 VREFA Output Bias voltage reference for the CLKA, nCLKA input pairs. 9 nCLKA Input [PD/PU] Inverting differential clock/data input. 10 CLKA Input [PD] Non-inverting differential clock/data input. 11 SELAA Input [PD/PU] Control input: Output amplitude select for channel A. 12 GND Power Power supply ground. 13 VDDQA Power Power supply pin for the channel A outputs QA[0:7]. 14 QA0 Output Differential output pair A0. LVDS interface levels. 15 nQA0 Output Differential output pair A0. LVDS interface levels. nQB6 nQB5 QB5 nQB4 QB4 nQB3 QB3 VDDQB nQB7 QB7 QB6 VDDQB QA1 QA2 nQA2 QA3 nQA3 QA4 nQA4 VDDQA QA0 nQA0 nQA1 VDDQA 12 34 56 789 10 11 12 24 23 22 21 20 19 18 16 17 15 14 13 37 38 39 40 41 42 43 45 44 46 47 48 36 35 34 33 32 31 30 29 28 27 26 25 8P34S2108 |
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