74LVC374AD datasheet(2/12 Pages) PHILIPS

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Philips Semiconductors

Product specification

74LVC374A

Octal D-type flip-flop with 5-volt tolerant

inputs/outputs; positive edge-trigger (3-State)

1998 Jul 29

853-1861 19802

FEATURES

• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

• Supply voltage range of 2.7V to 3.6V

• Complies with JEDEC standard no. 8-1A

• CMOS low power consumption

• Direct interface with TTL levels

• High impedance when V

CC = 0V

• 8-bit positive edge-triggered register

• Independent register and 3-State buffer operation

DESCRIPTION

The 74LVC374A is a high-performance, low-power, low-voltage,

Si-gate CMOS device, superior to most advanced CMOS

compatible TTL families.

Inputs can be driven from either 3.3V or 5V devices. In 3-State

operation, outputs can handle 5V. This feature allows the use of

these devices as translators in a mixed 3.3V/5V environment.

The 74LVC374A is an octal D-type flip-flop featuring separate

D-type inputs for each flip-flop and 3-State outputs for bus-oriented

applications. A clock (CP) and an output enable (OE) input are

common to all flip-flops.

The eight flip-flops will store the state of their individual D-inputs

that meet the setup and hold times requirements on the

LOW-to-HIGH CP transition.

When OE is LOW, the contents of the eight flip-flops is available at

the outputs. When OE is HIGH, the outputs go to the high

impedance OFF-state. Operation of the OE input does not affect the

state of the flip-flops.

The ’374’ is functionally identical to the ’574’, but the ’574’ has a

different pin arrangement.

QUICK REFERENCE DATA

GND = 0V; Tamb =25°C; tr = tf v 2.5ns

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

Propagation delay

CP to Qn

CL = 50pF

VCC = 3.3V

4.8

fmax

maximum clock frequency

150

MHz

Input capacitance

5.0

CPD

Power dissipation capacitance per

flip-flop

Notes 1 and 2

NOTE:

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

S (CL x VCC2 x fo) = sum of outputs.

2. The condition is VI = GND to VCC

ORDERING INFORMATION

PACKAGES

TEMPERATURE

RANGE

OUTSIDE

NORTH AMERICA

PKG. DWG. #

20-Pin Plastic Shrink Small Outline (SO)

–40

°C to +85°C

74LVC374A D

SOT163-1

20-Pin Plastic Shrink Small Outline (SSOP) Type II

–40

°C to +85°C

74LVC374A DB

SOT339-1

20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I

–40

°C to +85°C

74LVC374A PW

7LVC374APW DH

SOT360-1

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