74LVC573AD datasheet(2/12 Pages) PHILIPS

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Philips Semiconductors

Product specification

74LVC573A

Octal D-type transparent latch with 5-volt

tolerant inputs/outputs (3-State)

1998 Jul 29

853-1862 19804

FEATURES

• 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

• Supply voltage range of 2.7V to 3.6V

• Complies with JEDEC standard no. 8-1A

• Inputs accept voltages up to 5.5V

• CMOS low power consumption

• Direct interface with TTL levels

• High impedance when V

CC = 0V

• Flow-through pin-out architecture

DESCRIPTION

The 74LVC573A is a high-performance, low-power, low-voltage,

Si-gate CMOS device, superior to most advanced CMOS

compatible TTL families.

Inputs can be driven from either 3.3V or 5V devices. In 3-State

operation, outputs can handle 5V. This feature allows the use of

these devices as translators in a mixed 3.3V/5V environment.

The 74LVC573A is an octal D-type transparent latch featuring

separate D-type inputs for each latch and 3-State outputs for

bus-oriented applications. A latch enable (LE) input and an output

enable (OE) input are common to all internal latches.

The ’573A’ consists of eight D-type transparent latches with 3-State

true outputs. When LE is HIGH, data at the Dn inputs enters the

latches. In this condition, the latches are transparent, i.e. a latch

output will change each time its corresponding D-input changes.

When LE is LOW, the latches store the information that was present

at the D-inputs one setup time preceding the HIGH-to-LOW

transition of LE. When OE is LOW, the contents of the eight latches

are available at the outputs. When OE is HIGH, the outputs go to the

high impedance OFF-state. Operation of the OE input does not

affect the state of the latches.

The ’573A’ is functionally identical to the ’373A’, but the ’373A’ has a

different pin arrangement.

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

tPHL/tPLH

Propagation delay

Dn to Qn;

LE to Qn

CL = 50pF

VCC = 3.3V

4.3

4.6

Input capacitance

5.0

CPD

Power dissipation capacitance per latch

Notes 1 and 2

NOTE:

1. CPD is used to determine the dynamic power dissipation (PD in mW):

PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where:

fi = input frequency in MHz; CL = output load capacity in pF;

fo = output frequency in MHz; VCC = supply voltage in V;

S (CL x VCC2 x fo) = sum of outputs.

2. The condition is VI = GND to VCC

ORDERING INFORMATION

PACKAGES

TEMPERATURE

RANGE

OUTSIDE

NORTH AMERICA

PKG. DWG. #

20-Pin Plastic Shrink Small Outline (SO)

–40

°C to +85°C

74LVC573A D

SOT163-1

20-Pin Plastic Shrink Small Outline (SSOP) Type II

–40

°C to +85°C

74LVC573A DB

SOT339-1

20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I

–40

°C to +85°C

74LVC573A PW

7LVC573APW DH

SOT360-1

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